Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices. Most electronic devices are designed with a single flash memory device.
Flash memory devices typically use Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) cells, also referred to as fuses, to store device information. This information may include the address of defective memory array columns or rows and analog circuit configuration. The fuses are associated with latches in order to make the data stored in the fuse constantly available without the need for a typical flash memory read operation through the sense amplifiers.
FIG. 1 illustrates a schematic diagram of a typical prior art fuse and latch. In this scheme, the READ signal for the n-channel transistor 105 is normally in a logical low state. This turns off the transistor 105 and isolates the fuse 101. The signal FUSE—CLEAR is low to turn off the n-channel transistor 103, making it not effective. The signal PRE—CHARGE is high to turn off the p-channel transistor 113, making it not effective. The signal FSLTCH—BIAS is an analog signal that assumes a value between Vcc and Vss. That signal is normally low to turn on p-channel transistor 111, allowing the latch made by the inverter 107 and by the transistors 109 and 110, to be properly supplied by Vcc. To read the fuse 101, the signals PRE—CHARGE, FSLTCH—BIAS and READ are operated in sequence in two separate time intervals. In the first time interval, usually referred to as the precharge operation, while the READ and FSLTCH—BIAS signals are still low, the signal PRE—CHARGE goes low and therefore the p-channel transistor 113 is turned on to force the node OUTB at Vcc. Therefore the inverter 107, having at its input Vcc, turns low (Vss) the node OUT and this, throughout the transistors 109 and 110, confirms (latches) the node OUTB ad Vcc. In the second time interval, usually referred to as the sensing operation, the signal PRE—CHARGE goes back high, so that the p-channel transistor 113 is turned off, while the signal READ goes high, so that the n-channel 105 transistor is turned on to connect the fuse 101 to the latch structure. In addition, during the second time interval the signal FSLTCH—BIAS goes to an intermediate value between Vss and Vcc, so that the p-channel transistor 111 is still turned on, while its capability to conduct current is strongly reduced. That way, the series of the two p-channel transistors 111 and 109 will not be able to contrast the current eventually driven by the fuse 101 and flowing throughout the n-channel transistor 105. If the fuse 101 is programmed, a low current will flow from Vcc to Vss throughout the transistors 111, 109, 105 and the fuse 101 and a logical low signal is at the input of the inverter 107. Therefore, the latch transistors 109 and 110 receive a logical high output from the inverter 107 and confirm (latch) the logical low at node OUTB. If the fuse 101 is erased no current flows through it, the latch transistors 109 and 110 receive a logical low from the inverter 107 and confirm (latch) the logical high at node OUTB.
When the prior art circuit of FIG. 1 must be cleared (this usually happens during testing operations only, while still in the factory), the fuse—clear signal is brought to a logical high to turn on the n-channel transistor 103, while the signal PRE—CHARGE is maintained high to turn off transistor 113. This allows current to flow from Vcc through the p-channel transistors 111 and 109 and the n-channel transistor 103 to ground. This provides a logical high to the latch transistors 109 and 110, thus placing the latch into a default “erased” state before it receives its proper value from the fuse 101.
When a reset operation of the device occurs, both at power up and when the user applies to the device the proper reset pulse, this usually requires that, the latch must be reloaded with the proper (“erased” or “programmed”) data from the fuse 101. This managed, as explained above, in two distinct time intervals, is commonly referred to as the precharge and the sensing operations. The precharge operation reduces the speed at which the memory can respond after a reset condition has been experienced. An additional problem is that if a reset pulse is stopped too early for some reason, the proper value may not be reloaded into the latch and this error condition may not be detectable before causing additional errors to occur from the corrupted latch data.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a fuse and latch circuit that does not require a precharge operation.